Microcomputer Components 16-Bit CMOS Single-Chip Microcontroller ht Data Sheet 02.98 Preliminary tp :/ Se /ww m w ic .s on ie du me ct ns or .d / e/ C164CI C164CI Revision History: 1998-02 Preliminary Previous Releases: 04.97 (Advance Information) Page Subjects 3, 4 Alternate functions for P5 added. 25...30 Register Table updated. 32, 33 IP6H and IP6L removed. 33, 34 Supply current specification improved. 33, 34 Idle supply current specification IIDO improved. (Referring to Revision 11.97) 39, 40 ADC specification improved. 49, 50 Description for READY removed. - "AC Characteristics Demultiplexed Bus" removed. - "AC Characteristics External Bus Arbitration" removed. Controller Area Network (CAN): License of Robert Bosch GmbH Edition 1998-02 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1998. All Rights Reserved. Attention please! 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For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. C16x-Family of High-Performance CMOS 16-Bit Microcontrollers C164CI Preliminary C164CI 16-Bit Microcontroller High Performance 16-bit CPU with 4-Stage Pipeline 100 ns Instruction Cycle Time at 20 MHz CPU Clock 500 ns Multiplication (16 x 16 bit), 1 s Division (32/16 bit) Enhanced Boolean Bit Manipulation Facilities Additional Instructions to Support HLL and Operating Systems Register-Based Design with Multiple Variable Register Banks Single-Cycle Context Switching Support Clock Generation via On-Chip PLL or via Direct or Prescaled Clock Input Up to 4 MBytes Linear Address Space for Code and Data 2 KByte On-Chip Internal RAM (IRAM) 64 KByte On-Chip OTP (C164CI-8EM) or ROM (C164CI-8RM) Programmable External Bus Characteristics for Different Address Ranges 8-Bit or 16-Bit External Data Bus Multiplexed External Address/Data Bus Four optional Chip Select Signals CS0 - CS3 1024 Bytes On-Chip Special Function Register Area Idle and Power Down Modes with Flexible Power Management 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) 16-Priority-Level Interrupt System with 32 Interrupt sources 8-Channel 10-bit A/D Converter with 9.7 s Conversion Time (8.2 s min.) 8-Channel 16-bit General Purpose Capture/Compare Unit (CAPCOM2) Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6) (3/6 Capture/Compare Channels and 1 Compare Channel) Two Serial Channels (Synchronous/Asynchronous and High-Speed Synchronous) Multi-Functional General Purpose Timer Unit with three 16-bit Timers On-Chip Full-CAN Interface (V2.0B active) with 15 Message Objects and Basic CAN Feature Up to 59 General Purpose I/O Lines Programmable Watchdog Timer and Oscillator Watchdog On-Chip Real Time Clock Ambient temperature range -40 to 125 C Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstrap Loader 80-Pin MQFP Package, 0.65 mm pitch This document describes the SAF-C164CI-8EM and the SAK-C164CI-8EM. For simplicity all versions are referred to by the term C164CI throughout this document. Semiconductor Group 3 1998-02 C164CI Introduction The C164CI is a new low cost derivative of the Siemens C166 Family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 8 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. It also provides on-chip ROM or OTP and clock generation via PLL. The C164CI derivative is especially suited for cost sensitive applications. VDD VSS PORT0 16 bit XTAL1 XTAL2 PORT1 16 bit RSTIN RSTOUT NMI Port 3 9 bit C164CI EA Port 4 6 bit Port 8 4 bit ALE RD WR Port 5 8 bit VAREF VAGND Figure 1 Logic Symbol Ordering Information The ordering code for Siemens microcontrollers provides an exact reference to the required product. This ordering code identifies: the derivative itself, ie. its function set the specified temperature range the package the type of delivery. For the available ordering codes for the C164CI please refer to the Product Information Microcontrollers", which summarizes all available microcontroller variants. Note: The ordering codes for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Semiconductor Group 4 1998-02 C164CI 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VAGND P5.3/AN3 P5.2/AN2 P5.1/AN1 P5.0/AN0 P8.3/CC19IO P8.2/CC18IO P8.1/CC17IO P8.0/CC16IO NMI RSTOUT RSTIN P1H.7/CC27IO P1H.6/CC26IO P1H.5/CC25IO P1H.4/CC24IO P1H.3/EX3IN/T7IN P1H.2/CC6POS2/EX2IN P1H.1/CC6POS1/EX1IN VDD Pin Configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 C164CI 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VSS P1H.0/CC6POS0/EX0IN P1L.7/CTRAP P1L.6/COUT63 VSS XTAL1 XTAL2 VDD P1L.5/COUT62 P1L.4/CC62 P1L.3/COUT61 P1L.2/CC61 P1L.1/COUT60 P1L.0/CC60 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 Vss VDD P4.3/A19/CS0 P4.5/A20/CAN_RxD P4.6/A21/CAN_TxD RD WR/WRL ALE VPP/EA P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7 P0H.0/AD8 P0H.1/AD9 P0H.2/AD10 VDD 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VAREF P5.4/AN4/T2EUD P5.5/AN5/T4EUD P5.6/AN6/T2IN P5.7/AN7/T4IN VSS VDD P3.4/T3EUD P3.6/T3IN P3.8/MRST P3.9/MTSR P3.10/TxD0 P3.11/RxD0 P3.12/BHE/WRH P3.13/SCLK P3.15/CLKOUT P4.0/A16/CS3 P4.1/A17/CS2 P4.2/A18/CS1 VSS Figure 2 Semiconductor Group 5 1998-02 C164CI Pin Definitions and Functions Symbol Pin Input (I) Number Output (O) Function P5.0 - P5.7 76 - 79, 2-5 I I I Port 5 is a 8-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as the (up to 8) analog input channels for the A/D converter, where P5.x equals ANx (Analog input channel x). The following pins of Port 5 also serve as timer inputs: P5.4 T2EUD GPT1 Timer T2 Ext.Up/Down Ctrl.Input P5.5 T4EUD GPT1 Timer T4 Ext.Up/Down Ctrl.Input P5.6 T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture P5.7 T4IN GPT1 Timer T4 Input for Count/Gate/Reload/Capture P3.4, P3.6, P3.8 - P3.13, P3.15 8, 9, 10 - 15, 16 I/O I/O I/O I/O I/O Port 3 is a 9-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. 8 9 10 11 12 13 14 I I I/O I/O O I/O O 15 16 I/O O 17 - 19, 22, 23 24 I/O I/O I/O I/O 17 O O ... O O O I O O P4.0 - P4.3 P4.5 - P4.6 ... 22 23 24 Semiconductor Group The following Port 3 pins also serve for alternate functions: P3.4 T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input P3.6 T3IN GPT1 Timer T3 Count/Gate Input P3.8 MRST SSC Master-Rec./Slave-Transmit I/O P3.9 MTSR SSC Master-Transmit/Slave-Rec. O/I P3.10 TXD0 ASC0 Clock/Data Output (Asyn./Syn.) P3.11 RXD0 ASC0 Data Input (Asyn.) or I/O (Syn.) Ext. Memory High Byte Enable Signal, P3.12 BHE Ext. Memory High Byte Write Strobe WRH P3.13 SCLK SSC Master Clock Outp./Slave Cl. Inp. P3.15 CLKOUT System Clock Output (=CPU Clock) Port 4 is a 6-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0 A16 Least Significant Segment Addr. Line Chip Select 3 Output CS3 ... ... ... P4.3 A19 Segment Address Line Chip Select 0 Output CS0 P4.5 A20 Segment Address Line, CAN_RxD CAN Receive Data Input P4.6 A21 Most Significant Segment Addr. Line, CAN_TxD CAN Transmit Data Output 6 1998-02 C164CI Pin Definitions and Functions (cont'd) Symbol Pin Input (I) Number Output (O) Function RD 25 O External Memory Read Strobe. RD is activated for every external instruction or data read access. WR / WRL 26 O External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. ALE 27 O Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. EA 28 I External Access Enable pin. A low level at this pin during and after Reset forces the C164CI to begin instruction execution out of external memory. A high level forces execution out of the internal ROM. Note: This pin also accepts the programming voltage for OTP versions of the C164CI. I/O PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address and data (AD) bus. Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: AD0 - AD7 AD0 - AD7 P0H.0 - P0H.7: A8 - A15 AD8 - AD15 PORT0: P0L.0 - P0L.7, P0H.0 P0H.7 29 36 37 - 39, 42 - 46 Semiconductor Group 7 1998-02 C164CI Pin Definitions and Functions (cont'd) Symbol PORT1: P1L.0 - P1L.7, P1H.0 P1H.7 Pin Input (I) Number Output (O) I/O Function 65 ... 68 I I I I I I I I I ... I PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. The following Port 1 pins also serve for alternate functions: P1L.0 CC60 CAPCOM6: Input / Output of Ch. 0 P1L.1 COUT60 CAPCOM6: Output of Channel 0 P1L.2 CC61 CAPCOM6: Input / Output of Ch. 1 P1L.3 COUT61 CAPCOM6: Output of Channel 1 P1L.4 CC62 CAPCOM6: Input / Output of Ch. 2 P1L.5 COUT62 CAPCOM6: Output of Channel 2 P1L.6 COUT63 Output of 10-bit Compare Channel CAPCOM6: Trap Input P1L.7 CTRAP CTRAP is an input pin with an internal pullup resistor. A low level on this pin switches the compare outputs of the CAPCOM6 unit to the logic level defined by software. CAPCOM6: Position 0 Input P1H.0 CC6POS0 EX0IN Fast External Interrupt 0 Input CAPCOM6: Position 1 Input P1H.1 CC6POS1 EX1IN Fast External Interrupt 1 Input CAPCOM6: Position 2 Input P1H.2 CC6POS2 EX2IN Fast External Interrupt 2 Input P1H.3 EX3IN Fast External Interrupt 3 Input T7IN CAPCOM2: Timer T7 Count Input P1H.4 CC24IO CAPCOM2: CC24 Capture Input ... ... ... P1H.7 CC27IO CAPCOM2: CC27 Capture Input XTAL1 55 I XTAL1: XTAL2 54 O RSTIN 69 I 47 - 52, 57 - 58 59, 62 - 68 47 48 49 50 51 52 57 58 59 62 63 64 I/O O I/O O I/O O O I Semiconductor Group Input to the oscillator amplifier and input to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the C164CI. An internal pullup resistor permits poweron reset using only a capacitor connected to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in register SYSCON) the RSTIN line is pulled low for the duration of the internal reset sequence upon a software or WDT reset. 1) 8 1998-02 C164CI Pin Definitions and Functions (cont'd) Symbol Pin Input (I) Number Output (O) RSTOUT 70 Function O Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. NMI 71 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C164CI to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. P8.0 - P8.3 72 75 I/O I/O 72 ... 75 I/O ... I/O Port 8 is a 4-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. The following Port 8 pins also serve for alternate functions: P8.0 CC16IO CAPCOM2: CC16 Cap.-In/Comp.Out ... ... ... P8.3 CC19IO CAPCOM2: CC19 Cap.-In/Comp.Out VAREF 1 - Reference voltage for the A/D converter. VAGND 80 - Reference ground for the A/D converter. VDD 7, 21, 40, 53, 61 - Digital Supply Voltage: + 3 V / + 5 V during normal operation and idle mode. 2.5 V during power down mode VSS 6, 20, 41, 56, 60 - Digital Ground. 1) The following behaviour differences must be observed when the bidirectional reset is active: Bit BDRSTEN in register SYSCON cannot be changed after EINIT. After a reset bit BDRSTEN is cleared. Bit WDTR will always be '0', even after a watchdog timer reset. The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap loader may be activated when P0L.4 is low. Pin RSTIN may only be connected to external reset devices with an open drain output driver. Semiconductor Group 9 1998-02 C164CI Functional Description The C164CI is a low cost downgrade of the high performance microcontroller C167CR with OTP or internal ROM, reduced peripheral functionality and a high performance Capture Compare Unit with an additional functionality. The architecture of the C164CI combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C164CI. Note: All time specifications refer to a CPU clock of 20 MHz (see definition in the AC Characteristics section). C166-Core 16 Dual Port 64K Internal ROM (C164CI-8RM) or OTP (C164CI-8EM) Internal RAM 2 KByte RTC WDT Data 32 16 CPU Core CPU Instr./Data Data 16 PLL-Oscillator 16 up to 12 ext. IR Interrupt Bus 16 Peripheral Data External Bus (8/16 bit; MUX only) & XBUS Control 8Channel 10-Bit ADC USART Sync. Channel (SPI) GPT 1 ASC SSC T3 BRG BRG T4 T2 General Purpose Capture/Compare Unit 8-Channel 16-bit Capture/Compare Unit (CAPCOM2) Capture/Compare Unit for PWM Generation (CAPCOM6) Timer 13 Port 0 16 Interrupt Controller Timer 8 Full-CAN Interface V2.0B active PEC External Instr./Data Timer 7 P4.5/CAN_RxD P4.6/CAN_TxD progr. Multiplier: 0.5; 1; 1.5; 2; 2.5; 3; 4; 5 XBUS (16-bit NON MUX Data / Addresses) XTAL 1 Compare Channel 3/6 Capture/Compare Channels 5 Port 4 Port 5 Port 3 8 9 Port 8 Port 1 C164CI V1.2 4 16 Figure 3 Block Diagram Semiconductor Group 10 1998-02 C164CI Memory Organization The memory space of the C164CI is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 4 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable. The C164CI incorporates 64 KByte of on-chip ROM or OTP memory for code or constant data. The OTP memory can be programmed by the CPU itself (in system, eg. during booting) or directly via an external interface (eg. before assembly). The programming time is approx. 100 sec per word. An external programming voltage VPP = 11.5 V must be supplied for this purpose (via pin EA). 2 KBytes of on-chip Internal RAM are provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7) so-called General Purpose Registers (GPRs). 1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C16x family. In order to meet the needs of designs where more memory is required than is provided on chip, up to 4 MBytes of external RAM and/or ROM can be connected to the microcontroller. External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of two different external memory access modes, which are as follows: - 16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed - 16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed Important timing characteristics of the external bus interface (Memory Cycle Time, Memory TriState Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals. In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx / BUSCONx) which allow to access different resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. For applications which require less than 4 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no address lines at all. It outputs all 6 address lines, if an address space of 4 MBytes is used. Note: When the on-chip CAN Module is to be used the segment address output on Port 4 must be limited to 4 bits (ie. A19...A16) in order to enable the alternate function of the CAN interface pins. Semiconductor Group 11 1998-02 C164CI Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C164CI's instructions can be executed in just one machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 x 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so-called `Jump Cache', allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle. CPU Internal RAM SP STKOV STKUN MDH MDL R15 Exec. Unit Instr. Ptr. Instr. Reg. Mul/Div-HW Bit-Mask Gen General 4-Stage Pipeline R15 Purpose ALU 32 ROM 16 (16-bit) Barrel - Shifter Registers R0 PSW SYSCON Context Ptr. BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Data Page Ptr. Code Seg. Ptr. R0 16 MCB02147 Figure 4 CPU Block Diagram Semiconductor Group 12 1998-02 C164CI The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C164CI instruction set which includes the following instruction classes: - - - - - - - - - - - - Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands. Semiconductor Group 13 1998-02 C164CI Interrupt System With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal program execution), the C164CI is capable of reacting very fast to the occurrence of nondeterministic events. The architecture of the C164CI supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C164CI has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. The following table shows all of the possible C164CI interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Source of Interrupt or PEC Service Request Request Flag Enable Flag Interrupt Vector Vector Location Trap Number Fast External Interrupt 0 CC8IR CC8IE CC8INT 00'0060 H 18H Fast External Interrupt 1 CC9IR CC9IE CC9INT 00'0064H 19H Fast External Interrupt 2 CC10IE CC10IE CC10INT 00'0068H 1AH Fast External Interrupt 3 CC11IE CC11IE CC11INT 00'006CH 1BH GPT1 Timer 2 T2IR T2IE T2INT 00'0088H 22H GPT1 Timer 3 T3IR T3IE T3INT 00'008CH 23H Semiconductor Group 14 1998-02 C164CI Source of Interrupt or PEC Service Request Request Flag Enable Flag Interrupt Vector Vector Location Trap Number GPT1 Timer 4 T4IR T4IE T4INT 00'0090H 24H A/D Conversion Complete ADCIR ADCIE ADCINT 00'00A0 28H A/D Overrun Error ADEIR ADEIE ADEINT 00'00A4 29H ASC0 Transmit S0TIR S0TIE S0TINT 00'00A8H 2AH ASC0 Receive S0RIR S0RIE S0RINT 00'00ACH 2BH ASC0 Error S0EIR S0EIE S0EINT 00'00B0H 2CH SSC Transmit SCTIR SCTIE SCTINT 00'00B4H 2DH SSC Receive SCRIR SCRIE SCRINT 00'00B8H 2EH SSC Error SCEIR SCEIE SCEINT 00'00BCH 2FH CAPCOM Register 16 CC16IR CC16IE CC16INT 00'00C0H 30H CAPCOM Register 17 CC17IR CC17IE CC17INT 00'00C4H 31H CAPCOM Register 18 CC18IR CC18IE CC18INT 00'00C8H 32H CAPCOM Register 19 CC19IR CC19IE CC19INT 00'00CCH 33H CAPCOM Register 24 CC24IR CC24IE CC24INT 00'00E0H 38H CAPCOM Register 25 CC25IR CC25IE CC25INT 00'00E4H 39H CAPCOM Register 26 CC26IR CC26IE CC426NT 00'00E8H 3AH CAPCOM Register 27 CC27IR CC27IE CC27INT 00'00ECH 3BH CAPCOM Timer 7 T7IR T7IE T7INT 00'00F4H 3DH CAPCOM Timer 8 T8IR T8IE T8INT 00'00F8H 3EH CAPCOM 6 Interrupt CC6IR CC6IE CC6INT 00'00FCH 3FH XPER Node 0 Int / CAN XP0IR XP0IE XP0INT 00'0100H 40H XPER Node 3 Int / PLL / T14 XP3IR XP3IE XP3INT 00'010CH 43H ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00'011CH 47H CAPCOM 6 Timer 12 T12IR T12IE T12INT 00'0134H 4DH CAPCOM 6 Timer 13 T13IR T13IE T13INT 00'0138H 4EH CAPCOM 6 Emergency CC6EIR CC6EIE CC6EINT 00'013CH 4FH Semiconductor Group 15 1998-02 C164CI The C164CI also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called `Hardware Traps'. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during runtime: Exception Condition Trap Flag Trap Vector Vector Location Trap Number Trap Priority RESET RESET RESET 00'0000H 00'0000H 00'0000H 00H 00H 00H III III III NMI STKOF STKUF NMITRAP 00'0008H STOTRAP 00'0010H STUTRAP 00'0018H 02H 04H 06H II II II UNDOPC PRTFLT BTRAP BTRAP 00'0028H 00'0028H 0AH 0AH I I ILLOPA BTRAP 00'0028H 0AH I ILLINA ILLBUS BTRAP BTRAP 00'0028H 00'0028H 0AH 0AH I I Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved [2CH - 3CH] [0BH - 0FH] Software Traps TRAP Instruction Any [00'0000H - 00'01FCH] in steps of 4H Semiconductor Group 16 Any [00H - 7FH] Current CPU Priority 1998-02 C164CI The Capture/Compare Unit CAPCOM2 The general purpose CAPCOM2 unit supports generation and control of timing sequences on up to 8 channels with a maximum resolution of 400 ns (at 20 MHz system clock). The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for the capture/ compare register array. Each dual purpose capture/compare register, which may be individually allocated to either CAPCOM timer and programmed for capture or compare function, has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (`capture'd) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode. Compare Modes Function Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated Mode 3 Pin set `1' on match; pin reset `0' on compare time overflow; only one compare event per timer period is generated Double Register Mode Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible. Registers CC16 & CC24 pin CC16IO Registers CC17 & CC25 pin CC17IO Registers CC18 & CC26 pin CC18IO Registers CC19 & CC27 pin CC19IO Semiconductor Group 17 1998-02 C164CI The Capture/Compare Unit CAPCOM6 f CPU Offset Register T12OF Compare Timer T12 16-Bit 1) Mode Select Register CC6MSEL CC Channel 0 CC60 Control Prescaler Period Register T12P CC Channel 1 CC61 CC Channel 2 CC62 Trap Register CTRAP Port Control Logic The CAPCOM6 unit supports generation and control of timing sequences on up to three 16-bit capture/compare channels plus one 10-bit compare channel. In compare mode the CAPCOM6 unit provides two output signals per channel which have inverted polarity and non-overlapping pulse transitions. The compare channel can generate a single PWM output signal and is further used to modulate the capture/compare output signals. In capture mode the contents of compare timer 12 is stored in the capture registers upon a signal transition at pins CCx. For motor control applications both subunits may generate versatile multichannel PWM signals which are basically either controlled by compare timer 12 or by a typical hall sensor pattern at the interrupt inputs (block commutation). Compare timers 12 (16-bit) and 13 (10-bit) are free running timers which are clocked by the prescaled CPU clock. CC60 COUT60 CC61 COUT61 CC62 COUT62 Prescaler Control Register CTCON f CPU Compare Timer T13 10-Bit 1) Compare Register CMP13 Block Commutation Control CC6M CON.H Period Register T13P 1) COUT63 These Registers are not direct accessable. The period and offset registers are loading a value into the timer registers. CC6POS0 CC6POS1 CC6POS2 MCB03700 Figure 5 CAPCOM6 Block Diagram Semiconductor Group 18 1998-02 C164CI General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates three 16-bit timers. Each timer may operate independently in a number of different modes, or may be concatenated with another timer. Timer T3 can be configured for one of four basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode. Timers T2 and T4 can only be operated in timer mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes the associated port pin (T3IN) serves as gate or clock input. The maximum resolution of the timers is 400 ns (@ 20 MHz CPU clock). The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on pin T3EUD for T3 to facilitate eg. position tracking. In Incremental Interface Mode timer T3 can be directly connected to the incremental position sensor signals A and B via the respective inputs T3IN and T3EUD. Direction and count signals are internally derived from these two input signals, so the contents of timer T3 corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-flow/ underflow. The state of this latch may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload registers for timer T3. When used as reload registers, timers T2 and T4 are stopped. Timer T3 is reloaded with the contents of T2 or T4 triggered by a selectable state transition of its toggle latch T3OTL. Semiconductor Group 19 1998-02 C164CI X Figure 6 GPT Block Diagram Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 25 s and 420 ms can be monitored (@ 20 MHz). The default Watchdog Timer interval after reset is 6.55 ms (@ 20 MHz). Semiconductor Group 20 1998-02 C164CI Real Time Clock The Real Time Clock (RTC) module of the C164CI consists of a chain of 3 divider blocks, a fixed 8bit divider, the reloadable 16-bit timer T14 and the 32-bit RTC timer (accessible via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip oscillator frequency divided by 32 via a separate clock driver and is therefore independent from the selected clock generation mode of the C164CI. All timers count up. The RTC module can be used for different purposes: System clock to determine the current time and date Cyclic time based interrupt 48-bit timer for long term measurements T14REL Reload T14 8:1 fRTC Interrupt Request RTCL RTCL Figure 6-1 RTC Block Diagram Note: The register associated with the RTC are not effected by a reset in order to maintain the correct system time even when intermediate resets are executed. Semiconductor Group 21 1998-02 C164CI A/D Converter For analog signal measurement, a 10-bit A/D converter with 8 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry. Overrun error detection/protection is provided for the conversion result register (ADDAT): either an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended in such a case until the previous result has been read. For applications which require less than 8 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the C164CI supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. In addition, the conversion of a specific channel can be inserted (injected) into a running sequence without disturbing this sequence. This is called Channel Injection Mode. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. After each reset and also during normal operation the ADC automatically performs calibration cycles. This automatic self-calibration constantly adjusts the converter to changing operating conditions (eg. temperature) and compensates process variations. These calibration cycles are part of the conversion cycle, so they do not affect the normal operation of the A/D converter. Semiconductor Group 22 1998-02 C164CI Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/ Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with the serial ports of the Siemens 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 625 KBaud and half-duplex synchronous communication at up to 2.5 MBaud @ 20 MHz CPU clock. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 4 separate interrupt vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. The SSC supports full-duplex synchronous communication at up to 5 Mbaud @ 20 MHz CPU clock. It may be configured so it interfaces with serially linked peripheral components. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 3 separate interrupt vectors are provided. The SSC transmits or receives characters of 2...16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock edges as well as the clock polarity. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. Transmit and receive error supervise the correct handling of the data buffer. Phase and baudrate error detect incorrect serial data. Semiconductor Group 23 1998-02 C164CI CAN-Module The integrated CAN-Module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active), ie. the on-chip CANModule can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The module provides Full CAN functionality on up to 15 message objects. Message object 15 may be configured for Basic CAN functionality. Both modes provide separate masks for acceptance filtering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard a number of identifiers in Basic CAN mode. All message objects can be updated independent from the other objects and are equipped for the maximum message length of 8 bytes. The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud. The CAN-Module uses two pins of Port 4 to interface to a bus transceiver. Note: When the CAN interface is to be used the segment address output on Port 4 must be limited to 4 bits, ie. A19...A16. This is necessary to enable the alternate function of the CAN interface pins. Parallel Ports The C164CI provides up to 59 IO lines which are organized into five input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of two IO ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. All port lines have programmable alternate input or output functions associated with them. PORT0 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A21/19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Ports P1L, P1H and P8 are associated with the capture inputs or compare outputs of the CAPCOM units and/or serve as external interrupt inputs. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is used for the analog input channels to the A/D converter. All port lines that are not used for these alternate functions may be used as general purpose IO lines. Semiconductor Group 24 1998-02 C164CI Instruction Set Summary The table below lists the instructions of the C164CI in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the "C16x Family Instruction Set Manual". This document also provides a detailled description of each instruction. Instruction Set Summary Mnemonic Description Bytes ADD(B) Add word (byte) operands 2/4 ADDC(B) Add word (byte) operands with Carry 2/4 SUB(B) Subtract word (byte) operands 2/4 SUBC(B) Subtract word (byte) operands with Carry 2/4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2 DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2 DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2 CPL(B) Complement direct word (byte) GPR 2 NEG(B) Negate direct word (byte) GPR 2 AND(B) Bitwise AND, (word/byte operands) 2/4 OR(B) Bitwise OR, (word/byte operands) 2/4 XOR(B) Bitwise XOR, (word/byte operands) 2/4 BCLR Clear direct bit 2 BSET Set direct bit 2 BMOV(N) Move (negated) direct bit to direct bit 4 BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4 BCMP Compare direct bit to direct bit 4 BFLDH/L Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data 4 CMP(B) Compare word (byte) operands 2/4 CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2/4 CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2/4 PRIOR Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR 2 SHL / SHR Shift left/right direct word GPR 2 ROL / ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2 Semiconductor Group 25 1998-02 C164CI Instruction Set Summary (cont'd) Mnemonic Description Bytes MOV(B) Move word (byte) data 2/4 MOVBS Move byte operand to word operand with sign extension 2/4 MOVBZ Move byte operand to word operand. with zero extension 2/4 JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4 JMPS Jump absolute to a code segment 4 J(N)B Jump relative if direct bit is (not) set 4 JBC Jump relative and clear bit if direct bit is set 4 JNBS Jump relative and set bit if direct bit is not set 4 CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met 4 CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call absolute subroutine 4 TRAP Call interrupt service routine via immediate trap number 2 PUSH, POP Push/pop direct word register onto/from system stack 2 SCXT Push direct word register onto system stack und update register with word operand 4 RET Return from intra-segment subroutine 2 RETS Return from inter-segment subroutine 2 RETP Return from intra-segment subroutine and pop direct word register from system stack 2 RETI Return from interrupt service subroutine 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Enter Power Down Mode (supposes NMI-pin being low) 4 SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End-of-Initialization on RSTOUT-pin 4 ATOMIC Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2 EXTP(R) Begin EXTended Page (and Register) sequence 2/4 EXTS(R) Begin EXTended Segment (and Register) sequence 2/4 NOP Null operation 2 Semiconductor Group 26 1998-02 C164CI Special Function Registers Overview The following table lists all SFRs which are implemented in the C164CI in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers). Name Physical 8-Bit Address Address Description Reset Value ADCIC b FF98H CCH A/D Converter End of Conversion Interrupt Control Register 0000H ADCON b FFA0H D0H A/D Converter Control Register 0000H ADEIC b FF9AH CDH A/D Converter Overrun Error Interrupt Control Register 0000H 50H A/D Converter Result Register 0000H ADDAT FEA0H ADDAT2 F0A0H E 50H A/D Converter 2 Result Register 0000H ADDRSEL1 FE18H 0CH Address Select Register 1 0000H ADDRSEL2 FE1AH 0DH Address Select Register 2 0000H ADDRSEL3 FE1CH 0EH Address Select Register 3 0000H ADDRSEL4 FE1EH 0FH Address Select Register 4 0000H BUSCON0 b FF0CH 86H Bus Configuration Register 0 0000H BUSCON1 b FF14H 8AH Bus Configuration Register 1 0000H BUSCON2 b FF16H 8BH Bus Configuration Register 2 0000H BUSCON3 b FF18H 8CH Bus Configuration Register 3 0000H BUSCON4 b FF1AH 8DH Bus Configuration Register 4 0000H C1BTR EF04H X --- CAN Bit Timing Register UUUUH C1CSR EF00H X --- CAN Control / Status Register C1GMS EF06H X --- CAN Global Mask Short C1IR EF02H X --- CAN Interrupt Register C1LGML EF0AH X --- CAN Lower Global Mask Long UUUUH C1LMLM EF0EH X --- CAN Lower Mask of Last Message UUUUH C1UGML EF08H X --- CAN Upper Global Mask Long UUUUH C1UMLM EF0CH X --- CAN Upper Mask of Last Message UUUUH XX01H UFUUH XXH CC10IC b FF8CH C6H CAPCOM Register 10 Interrupt Control Register 0000H CC11IC b FF8EH C7H CAPCOM Register 11 Interrupt Control Register 0000H Semiconductor Group 27 1998-02 C164CI Name Physical 8-Bit Address Address Description CC16 FE60H CAPCOM Register 16 0000H CAPCOM Register 16 Interrupt Control Register 0000H CAPCOM Register 17 0000H CAPCOM Register 17 Interrupt Control Register 0000H CAPCOM Register 18 0000H CAPCOM Register 18 Interrupt Control Register 0000H CAPCOM Register 19 0000H CAPCOM Register 19 Interrupt Control Register 0000H CAPCOM Register 24 0000H CAPCOM Register 24 Interrupt Control Register 0000H CAPCOM Register 25 0000H CAPCOM Register 25 Interrupt Control Register 0000H CAPCOM Register 26 0000H CAPCOM Register 26 Interrupt Control Register 0000H CAPCOM Register 27 0000H CAPCOM Register 27 Interrupt Control Register 0000H CC16IC CC17 CC17IC CC18 CC18IC CC19 CC19IC CC24 CC24IC CC25 CC25IC CC26 CC26IC CC27 CC27IC 30H b F160H E B0H FE62H 31H b F162H E B1H FE64H 32H b F164H E B2H FE66H 33H b F166H E B3H FE70H 38H b F170H E B8H FE72H 39H b F172H E B9H FE74H 3AH b F174H E BAH FE76H 3BH b F176H E BBH Reset Value CC60 FE30H 18H CAPCOM 6 Register 0 0000H CC61 FE32H 19H CAPCOM 6 Register 1 0000H CC62 FE34H 1AH CAPCOM 6 Register 2 0000H CC6EIC b F188H E C4H CAPCOM 6 Emergency Interrupt Control Reg. 0000H CC6IC b F17EH E BFH CAPCOM 6 Interrupt Control Register 0000H CC6MCON b FF32H 99H CAPCOM 6 Mode Control Register 00FFH CC6MIC 9BH CAPCOM 6 Mode Interrupt Control Register 0000H CAPCOM 6 Mode Select Register 0000H CC6MSEL b FF36H F036H E 1BH CC8IC b FF88H C4H CAPCOM Register 8 Interrupt Control Register 0000H CC9IC b FF8AH C5H CAPCOM Register 9 Interrupt Control Register 0000H CCM4 b FF22H 91H CAPCOM Mode Control Register 4 0000H CCM6 b FF26H 93H CAPCOM Mode Control Register 6 0000H CMP13 FE36H 1BH CAPCOM 6 Timer 13 Compare Register 0000H CP FE10H 08H CPU Context Pointer Register FC00H CSP FE08H 04H CPU Code Segment Pointer Register (8 bits, not directly writeable) 0000H b FF30H 98H CAPCOM 6 Compare Timer Control Register 1010H CTCON Semiconductor Group 28 1998-02 C164CI Name Physical 8-Bit Address Address Description Reset Value DP0H b F102H E 81H P0H Direction Control Register 00H DP0L b F100H E 80H P0L Direction Control Register 00H DP1H b F106H E 83H P1H Direction Control Register 00H DP1L b F104H E 82H P1L Direction Control Register 00H DP3 b FFC6H E3H Port 3 Direction Control Register 0000H DP4 b FFCAH E5H Port 4 Direction Control Register 00H DP8 b FFD6H EBH Port 8 Direction Control Register 00H DPP0 FE00H 00H CPU Data Page Pointer 0 Register (10 bits) 0000H DPP1 FE02H 01H CPU Data Page Pointer 1 Register (10 bits) 0001H DPP2 FE04H 02H CPU Data Page Pointer 2 Register (10 bits) 0002H DPP3 FE06H 03H CPU Data Page Pointer 3 Register (10 bits) 0003H EXICON b F1C0H E E0H External Interrupt Control Register 0000H EXISEL b F1DAH E EDH External Interrupt Source Select Register 0000H IDCHIP F07CH E 3EH Identifier 0A01H IDMANUF F07EH E 3FH Identifier 1820H IDMEM F07AH E 3DH Identifier X010H IDPROG F078H E 3CH Identifier XXXXH ISNC b F1DEH E EFH Interrupt Subnode Control Register LAR EFn4H X --- CAN Lower Arbitration Register (msg. n) MCFG EFn6H X --- CAN Message Configuration Register (msg. n) MCR EFn0H X --- CAN Message Control Register (msg. n) 0000H UUUUH UUH UUUUH MDC b FF0EH 87H CPU Multiply Divide Control Register 0000H MDH FE0CH 06H CPU Multiply Divide Register - High Word 0000H MDL FE0EH 07H CPU Multiply Divide Register - Low Word 0000H ODP3 b F1C6H E E3H Port 3 Open Drain Control Register 0000H ODP8 b F1D6H E EBH Port 8 Open Drain Control Register 00H ONES b FF1EH Constant Value 1's Register (read only) FFFFH 8FH OPAD EDC2H X --- OTP Programming Interface Address Register 0000H OPCTRL EDC0H X --- OTP Programming Interface Control Register 0007H OPDAT EDC4H X --- OTP Programming Interface Data Register 0000H P0H b FF02H 81H Port 0 High Register (Upper half of PORT0) 00H P0L b FF00H 80H Port 0 Low Register (Lower half of PORT0) 00H P1H b FF06H 83H Port 1 High Register (Upper half of PORT1) 00H Semiconductor Group 29 1998-02 C164CI Name Physical 8-Bit Address Address Description Reset Value P1L b FF04H 82H Port 1 Low Register (Lower half of PORT1) 00H P3 b FFC4H E2H Port 3 Register P4 b FFC8H E4H Port 4 Register (8 bits) P5 b FFA2H D1H Port 5 Register (read only) P5DIDIS b FFA4H D2H Port 5 Digital Input Disable Register P8 b FFD4H EAH Port 8 Register (8 bits) PECC0 FEC0H 60H PEC Channel 0 Control Register 0000H PECC1 FEC2H 61H PEC Channel 1 Control Register 0000H PECC2 FEC4H 62H PEC Channel 2 Control Register 0000H PECC3 FEC6H 63H PEC Channel 3 Control Register 0000H PECC4 FEC8H 64H PEC Channel 4 Control Register 0000H PECC5 FECAH 65H PEC Channel 5 Control Register 0000H PECC6 FECCH 66H PEC Channel 6 Control Register 0000H PECC7 FECEH 67H PEC Channel 7 Control Register 0000H 0000H 00H XXXXH 0000H 00H PICON b F1C4H E E2H Port Input Threshold Control Register 0000H PSW b FF10H CPU Program Status Word 0000H RP0H b F108H E 84H RTCH F0D6H E 6BH RTC High Register XXXXH RTCL F0D4H E 6AH RTC Low Register XXXXH S0BG FEB4H 5AH Serial Channel 0 Baud Rate Generator Reload Register 0000H S0CON b FFB0H D8H Serial Channel 0 Control Register 0000H S0EIC b FF70H B8H Serial Channel 0 Error Interrupt Control Register 0000H FEB2H 59H Serial Channel 0 Receive Buffer Register (read only) XXXXH S0RIC b FF6EH B7H Serial Channel 0 Receive Interrupt Control Register 0000H S0TBIC b F19CH E CEH Serial Channel 0 Transmit Buffer Interrupt Control Register 0000H S0RBUF S0TBUF 88H System Startup Configuration Register (Rd. only) XXH FEB0H 58H Serial Channel 0 Transmit Buffer Register 0000H b FF6CH B6H Serial Channel 0 Transmit Interrupt Control Register 0000H SP FE12H 09H CPU System Stack Pointer Register FC00H SSCBR F0B4H E 5AH SSC Baudrate Register 0000H 30 1998-02 S0TIC Semiconductor Group C164CI Name Physical 8-Bit Address Address Description Reset Value SSCCON b FFB2H D9H SSC Control Register 0000H SSCEIC b FF76H BBH SSC Error Interrupt Control Register 0000H SSCRB SSCRIC SSCTB F0B2H E 59H b FF74H BAH F0B0H E 58H SSC Receive Buffer (read only) XXXXH SSC Receive Interrupt Control Register 0000H SSC Transmit Buffer (write only) 0000H SSCTIC b FF72H B9H SSC Transmit Interrupt Control Register 0000H STKOV FE14H 0AH CPU Stack Overflow Pointer Register FA00H STKUN FE16H 0BH CPU Stack Underflow Pointer Register FC00H b FF12H 89H CPU System Configuration Register SYSCON 0XX0H1) SYSCON2 b F1D0H E E8H CPU System Configuration Register 2 0000H SYSCON3 b F1D4H E EAH CPU System Configuration Register 3 0000H T12IC CAPCOM 6 Timer 12 Interrupt Control Register 0000H b F190H E C8H T12OF F034H E 1AH CAPCOM 6 Timer 12 Offset Register 0000H T12P F030H E 18H CAPCOM 6 Timer 12 Period Register 0000H CAPCOM 6 Timer 13 Interrupt Control Register 0000H 0000H T13IC b F198H E CCH T13P F032H E 19H CAPCOM 6 Timer 13 Period Register T14 F0D2H E 69H RTC Timer 14 Register XXXXH T14REL F0D0H E 68H RTC Timer 14 Reload Register XXXXH T2 FE40H 20H GPT1 Timer 2 Register 0000H T2CON b FF40H A0H GPT1 Timer 2 Control Register 0000H T2IC b FF60H B0H GPT1 Timer 2 Interrupt Control Register 0000H FE42H 21H GPT1 Timer 3 Register 0000H T3CON b FF42H A1H GPT1 Timer 3 Control Register 0000H T3IC b FF62H B1H GPT1 Timer 3 Interrupt Control Register 0000H FE44H 22H GPT1 Timer 4 Register 0000H T4CON b FF44H A2H GPT1 Timer 4 Control Register 0000H T4IC b FF64H B2H GPT1 Timer 4 Interrupt Control Register 0000H CAPCOM Timer 7 Register 0000H CAPCOM Timer 7 and 8 Control Register 0000H CAPCOM Timer 7 Interrupt Control Register 0000H T3 T4 T7 F050H E 28H T78CON b FF20H 90H T7IC b F17AH E BDH T7REL F054H E 2AH CAPCOM Timer 7 Reload Register 0000H T8 F052H E 29H CAPCOM Timer 8 Register 0000H CAPCOM Timer 8 Interrupt Control Register 0000H T8IC b F17CH E BEH Semiconductor Group 31 1998-02 C164CI Name Physical 8-Bit Address Address Description Reset Value T8REL F056H E 2BH CAPCOM Timer 8 Reload Register 0000H TFR b FFACH D6H Trap Flag Register 0000H TRCON b FF34H 9AH CAPCOM 6 Trap Enable Control Register 00XXH UUUUH UAR EFn2H X --- CAN Upper Arbitration Register (msg. n) WDT FEAEH 57H Watchdog Timer Register (read only) WDTCON b FFAEH D7H Watchdog Timer Control Register 0000H 00XXH2) XP0IC b F186H E C3H X-Peripheral 0 Interrupt Control Register 0000H XP3IC b F19EH E CFH X-Peripheral 3 Interrupt Control Register 0000H ZEROS b FF1CH Constant Value 0's Register (read only) 0000H 8EH 1) The system configuration is selected during reset. 2) The reset value depends on the indicated reset source. Semiconductor Group 32 1998-02 C164CI Absolute Maximum Ratings Ambient temperature under bias (TA): SAF-C164CI ................................................................................................................ -40 to +85 C SAK-C164CI .............................................................................................................. -40 to +125 C Storage temperature (TST)........................................................................................ - 65 to +150 C Voltage on VDD pins with respect to ground (VSS) ..................................................... -0.5 to +6.5 V Voltage on any pin with respect to ground ( VSS) .................................................-0.5 to VDD +0.5 V Input current on any pin during overload condition.................................................... -10 to +10 mA Absolute sum of all input currents during overload condition ..............................................|100 mA| Power dissipation..................................................................................................................... 1.5 W Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions ( VIN>VDD or VIN<VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C164CI and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the C164CI will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the C164CI. Semiconductor Group 33 1998-02 C164CI DC Characteristics VDD = 4.25 - 5.5 V; VSS = 0 V; fCPU = 20 MHz TA = -40 to +85 C for SAF-C164CI TA = -40 to +125 C for SAK-C164CI Parameter Symbol Limit Values min. Unit Test Condition 0.2 VDD - 0.1 V - max. Input low voltage (TTL) VIL Input low voltage (Special Threshold) VILS SR - 0.5 2.0 V - Input high voltage, all except RSTIN and XTAL1 (TTL) VIH SR 0.2 VDD + 0.9 VDD + 0.5 V - Input high voltage RSTIN VIH1 SR 0.6 VDD VDD + 0.5 V - Input high voltage XTAL1 VIH2 SR 0.7 VDD VDD + 0.5 V - Input high voltage (Special Threshold) VIHS SR 0.8 VDD VDD + 0.5 V - Input Hysteresis (Special Threshold) HYS - mV - Output low voltage VOL CC - (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) 0.45 V IOL = 2.4 mA VOL1 CC - 0.45 V IOL1 = 1.6 mA - V IOH = - 500 A IOH = - 2.4 mA - V V IOH = - 250 A IOH = - 1.6 mA SR - 0.5 - 0.2 Output low voltage (all other outputs) 400 Output high voltage VOH CC 0.9 VDD (PORT0, PORT1, Port 4, ALE, RD, 2.4 WR, BHE, CLKOUT, RSTOUT) 1) Output high voltage (all other outputs) VOH1 CC 0.9 VDD 2.4 Input leakage current (Port 5) IOZ1 CC - 200 nA 0.45V<VIN< VDD Input leakage current (all other) IOZ2 CC - 500 nA 0.45V<VIN< VDD Overload current IOV 5 mA 5) 8) RSTIN pullup resistor RRST CC 50 250 k - IRWH 2) - -40 A VOUT = 2.4 V IRWL 3) -500 - A VOUT = VOLmax IALEL 2) - 40 A VOUT = VOLmax IALEH 3) 500 - A VOUT = 2.4 V Read/Write inactive current Read/Write active current ALE inactive current ALE active current 4) 4) 4) 4) PORT0 configuration current Semiconductor Group 4) SR - IP0H 2) - -10 A VIN = VIHmin IP0L 3) -100 - A VIN = VILmax 34 1998-02 C164CI Parameter Symbol Limit Values min. XTAL1 input current 5) IIL CC - Unit Test Condition 20 A 0 V < VIN < VDD max. Pin capacitance (digital inputs/outputs) CIO CC - 10 pF f = 1 MHz TA = 25 C Power supply current (active) with all peripherals active IDD - 10 + 3.5 x fCPU mA RSTIN = VIL2 fCPU in [MHz] 6) Idle mode supply current with all peripherals active IIDX - 5+ 1.25 x fCPU mA RSTIN = VIH1 fCPU in [MHz] 6) Idle mode supply current with all peripherals deactivated, PLL off, SDD factor = 32 IIDO - 500 + A 9) 50 x fOSC RSTIN = VIH1 fCPU in [MHz] 6) Power-down mode supply current with RTC running IPDR - 100 + A 25 x fOSC 9) VDD = 5.5 V fOSC in [MHz] 7) Power-down mode supply current with RTC disabled IPDO - 50 A VDD = 5.5 V 7) Notes 1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 2) The maximum current may be drawn while the respective signal line remains inactive. 3) The minimum current must be drawn in order to drive the respective signal line active. 4) This specification is only valid during Reset, or during Adapt-mode. 5) Not 100% tested, guaranteed by design characterization. 6) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at VDDmax and 20 MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. The oscillator also contributes to the total supply current. The given values refer to the worst case, i.e. IPDRmax. For lower oscillator frequencies the respective supply current can be reduced accordingly. 7) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD - 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected. 8) Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload currents on all port pins may not exceed 50 mA. The supply voltage (VDD and VSS) must remain within the specified limits. 9) This parameter is determined mainly by the current consumed by the oscillator. This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry. A typical value for IPDR at room temperature and fOSC = 16 MHz is 300 A. Semiconductor Group 35 1998-02 I [mA] C164CI IDDmax 80 IDDtyp 40 IIDXmax IIDXtyp 10 5 10 15 20 fCPU [MHz] I [A] Figure 7 Active and Idle Supply Current as a Function of Operating Frequency 1500 IIDOmax 1250 1000 IIDOtyp 750 IPDRmax 500 250 IPDOmax 4 8 12 16 fOSC [MHz] Figure 8 Idle and Power Down Supply Current as a Function of Oscillator Frequency Semiconductor Group 36 1998-02 C164CI AC Characteristics Definition of Internal Timing The internal operation of the C164CI is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (eg. pipeline) or external (eg. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL" (see figure below). Phase Locked Loop Operation fXTAL fCPU TCL TCL Direct Clock Drive fXTAL fCPU TCL TCL Prescaler Operation fXTAL fCPU TCL TCL Figure 9 Generation Mechanisms for the CPU Clock The CPU clock signal can be generated via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to generate f CPU. This influence must be regarded when calculating the timings for the C164CI. Note: The example for PLL operation shown in the figure above refers to a PLL factor of 4. The used mechanism to generate the CPU clock is selected during reset via the logic levels on pins P0.15-13 (P0H.7-5). The table below associates the combinations of these three bits with the respective clock generation mode. Semiconductor Group 37 1998-02 C164CI C164CI Clock Generation Modes P0.15-13 (P0H.7-5) 1) 2) CPU Frequency fCPU = fXTAL * F External Clock Input Notes Range 1) 1 1 1 fXTAL * 4 2.5 to 5 MHz 1 1 0 fXTAL * 3 3.33 to 6.66 MHz 1 0 1 fXTAL * 2 5 to 10 MHz 1 0 0 fXTAL * 5 2 to 4 MHz 0 1 1 fXTAL * 1 1 to 20 MHz 0 1 0 fXTAL * 1.5 0 0 1 fXTAL / 2 2 to 40 MHz 0 0 0 fXTAL * 2.5 4 to 8 MHz Default configuration Direct drive 2) 6.66 to 13.3 MHz CPU clock via prescaler The external clock input range refers to a CPU clock range of 10...20 MHz. The maximum frequency depends on the duty cycle of the external clock signal. Prescaler Operation When pins P0.15-13 (P0H.7-5) equal '001' during reset the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (ie. the duration of an individual TCL) is defined by the period of the input clock f XTAL. The timings listed in the AC Characteristics that refer to TCLs therefore can be calculated using the period of fXTAL for any TCL. Direct Drive When pins P0.15-13 (P0H.7-5) equal '011' during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU (ie. the duration of an individual TCL) is defined by the duty cycle of the input clock f XTAL. The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula: TCLmin = 1/fXTAL * DCmin (DC = duty cycle) For two consecutive TCLs the deviation caused by the duty cycle of fXTAL is compensated so the duration of 2TCL is always 1/fXTAL. The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula 2TCL = 1/fXTAL. Note: The address float timings in Multiplexed bus mode (t 11 and t45) use the maximum duration of TCL (TCLmax = 1/fXTAL * DCmax) instead of TCLmin. Semiconductor Group 38 1998-02 C164CI Phase Locked Loop For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked loop is enabled and provides the CPU clock (see table above). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (ie. fCPU = fXTAL * F). With every F'th transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothely, ie. the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and figure below). For a period of N * TCL the minimum value is computed using the corresponding deviation DN: TCLmin = TCLNOM * (1 - DN / 100) DN = (4 - N /15) [%], where N = number of consecutive TCLs and 1 N 40. So for a period of 3 TCLs (ie. N = 3): D3 = 4 - 3/15 = 3.8%, and (3TCL)min = 3TCLNOM * (1 - 3.8 / 100) = 3TCLNOM * 0.962 (57.72 nsec @ fCPU = 25 MHz). This is especially important for bus cycles using waitstates and eg. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (eg. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible. Max.jitter [%] This approximated formula is valid for 1 N 40 and 10MHz fCPU 25MHz. 4 3 2 1 2 4 8 16 32 N Figure 10 Approximated Maximum PLL Jitter Semiconductor Group 39 1998-02 C164CI AC Characteristics External Clock Drive XTAL1 VDD = 4.25 - 5.5 V; TA = -40 to +85 C TA = -40 to +125 C VSS = 0 V for SAF-C164CI for SAK-C164CI Parameter Symbol Direct Drive 1:1 min. max. min. max. 8000 25 4000 75 1) 500 1) ns 6 - 10 - ns 6 - 10 - High time t1 SR 18 2) - t2 2) - 2) Rise time t3 SR - 10 Fall time t4 SR - 10 2) 1) 2) Unit min. tOSC SR 50 SR 18 PLL 1:N max. Oscillator period Low time Prescaler 2:1 - 6 2) - 6 2) ns - 10 2) ns - 10 2) ns The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation mode. Please see respective table above. The clock input signal must reach the defined levels VIL and VIH2. t1 t3 t4 VIH2 0.5 VCC VIL te t asc MCT02534 Figure 11 External Clock Drive XTAL1 Semiconductor Group 40 1998-02 C164CI A/D Converter Characteristics VDD = 4.25 - 5.5 V; VSS = 0 V TA = -40 to +85 C for SAF-C164CI TA = -40 to +125 C for SAK-C164CI 4.0 V VAREF VDD+0.1 V ; VSS-0.1 V VAGND VSS+0.2 V Parameter Symbol Limit Values min. Unit Test Condition max. Analog input voltage range VAIN SR VAGND VAREF V 1) Basic clock frequency fBC 6 MHz 2) Conversion time tC 0.5 3) 40 tBC + tS + 2 tCPU CC - tCPU = 1 / fCPU Total unadjusted error TUE CC - 2 LSB 4) Internal resistance of reference voltage source RAREF SR - tBC / 60 k tBC in [ns] 5) 6) Internal resistance of analog source RASRC SR - k tS in [ns] 6) 7) ADC input capacitance CAIN CC - pF 6) - 0.25 tS / 450 - 0.25 33 Sample time and conversion time of the C164CI's A/D Converter are programmable. The table below should be used to calculate the above timings. The limit values for fBC must not be exceeded when selecting ADCTC. ADCON.15|14 A/D Converter Basic clock (ADCTC) fBC 2) ADCON.13|12 Sample time tS 7) (ADSTC) 00 fCPU / 4 00 tBC * 8 01 fCPU / 2 01 tBC * 16 10 fCPU / 16 10 tBC * 32 11 fCPU / 8 11 tBC * 64 Converter Timing Example: Assumptions: fCPU = 20 MHz (ie. tCPU = 50 ns), ADCTC = '00', ADSTC = '00'. Basic clock fBC Sample time tS Conversion time tC Semiconductor Group = fCPU / 4 = 5 MHz, ie. tBC = 200 ns. = tBC * 8 = 1600 ns. = tS + 40 tBC + 2 tCPU = (1600 + 8000 + 100) ns = 9.7 s. 41 1998-02 C164CI Notes 1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. 2) The limit values for fBC must not be exceeded when selecting the CPU frequency and the ADCTC setting. 3) This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the basic clock tBC depend on programming and can be taken from the table above. This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum. 4) TUE is tested at VAREF=5.0V, VAGND=0V, VDD=4.9V. It is guaranteed by design for all other voltages within the defined voltage range. The specified TUE is guaranteed only if an overload condition (see IOV specification) occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA. During the reset calibration sequence the maximum TUE may be 4 LSB. 5) During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within each conversion step. The maximum internal resistance results from the programmed conversion timing. 6) Not 100% tested, guaranteed by design. 7) During the sample time the input capacitance CI can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample time tS depend on programming and can be taken from the table above. Semiconductor Group 42 1998-02 C164CI Testing Waveforms AC inputs during testing are driven at 2.4 V for a logic `1' and 0.45 V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'. Figure 12 Input Output Waveforms For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20 mA). Figure 13 Float Waveforms Semiconductor Group 43 1998-02 C164CI Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Description Symbol Values ALE Extension tA TCL * <ALECTL> Memory Cycle Time Waitstates tC 2TCL * (15 - <MCTC>) Memory Tristate Time tF 2TCL * (1 - <MTTC>) AC Characteristics Multiplexed Bus VDD = 4.25 - 5.5 V; VSS = 0 V TA = -40 to +85 C for SAF-C164CI TA = -40 to +125 C for SAK-C164CI CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. min. Unit max. CC 15 + tA - TCL - 10 + tA - ns Address setup to ALE t5 t6 CC 9 + tA - TCL - 16 + tA - ns Address hold after ALE t7 CC 15 + tA - TCL - 10 + tA - ns ALE falling edge to RD, WR (with RW-delay) t8 CC 15 + tA - TCL - 10 + tA - ns ALE falling edge to RD, WR (no RW-delay) t9 CC -10 + tA - -10 + tA - ns Address float after RD, WR (with RW-delay) t10 CC - 6 - 6 ns Address float after RD, WR (no RW-delay) t11 CC - 31 - TCL + 6 ns RD, WR low time (with RW-delay) t12 CC 40 + tC - 2TCL - 10 + tC - ns RD, WR low time (no RW-delay) t13 CC 65 + tC - 3TCL - 10 + tC - ns RD to valid data in (with RW-delay) t14 SR - 30 + tC - 2TCL - 20 + tC ns ALE high time Semiconductor Group 44 1998-02 C164CI Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. min. max. Unit RD to valid data in (no RW-delay) t15 SR - 55 + tC - 3TCL - 20 + tC ns ALE low to valid data in t16 SR - 55 + tA + tC - 3TCL - 20 + tA + tC ns Address to valid data in t17 SR - 70 + 2t A + t C - 4TCL - 30 + 2tA + tC ns Data hold after RD rising edge t18 SR 0 - 0 - ns Data float after RD t19 SR - 36 + tF - 2TCL - 14 + tF ns Data valid to WR t22 CC 30 + tC - 2TCL - 20 + tC - ns Data hold after WR t23 CC 36 + tF - 2TCL - 14 + tF - ns ALE rising edge after RD, WR t25 CC 36 + tF - 2TCL - 14 + tF - ns Address hold after RD, WR t27 CC 36 + tF - 2TCL - 14 + tF - ns ALE falling edge to CS t38 CC -4 - tA 10 - tA -4 - tA 10 - tA ns CS low to Valid Data In t39 SR - 55 + tC + 2tA - 3TCL - 20 + tC + 2tA ns CS hold after RD, WR t40 CC 61 + tF - 3TCL - 14 + tF - ns ALE fall. edge to RdCS, WrCS (with RW delay) t42 CC 21 + tA - TCL - 4 + tA - ns ALE fall. edge to RdCS, WrCS (no RW delay) t43 CC -4 + tA - -4 + tA - ns Address float after RdCS, WrCS (with RW delay) t44 CC - 0 - 0 ns Address float after RdCS, WrCS (no RW delay) t45 CC - 25 - TCL ns RdCS to Valid Data In (with RW delay) t46 SR - 26 + tC - 2TCL - 24 + tC ns RdCS to Valid Data In (no RW delay) t47 SR - 51 + tC - 3TCL - 24 + tC ns Semiconductor Group 45 1998-02 C164CI Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. min. max. Unit RdCS, WrCS Low Time (with RW delay) t48 CC 40 + tC - 2TCL - 10 + tC - ns RdCS, WrCS Low Time (no RW delay) t49 CC 65 + tC - 3TCL - 10 + tC - ns Data valid to WrCS t50 CC 36 + tC - 2TCL - 14 + tC - ns Data hold after RdCS t51 SR 0 - 0 - ns Data float after RdCS t52 SR - 30 + tF - 2TCL - 20 + tF ns Address hold after RdCS, WrCS t54 CC 30 + tF - 2TCL - 20 + tF - ns Data hold after WrCS t56 CC 30 + tF - 2TCL - 20 + tF - ns Semiconductor Group 46 1998-02 C164CI t5 t16 t25 ALE t38 t39 t40 CSx t17 A23-A16 (A15-A8) BHE t27 Address t6 t7 t54 t19 Read Cycle BUS t18 Address t8 Data In t10 t14 RD t42 t44 t12 t51 t52 t46 RdCSx t48 Write Cycle BUS t23 Address t8 Data Out t56 t10 t22 WR, WRL, WRH t42 t12 t44 t50 WrCSx t48 Figure 14-1 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group 47 1998-02 C164CI t5 t16 t25 t39 t40 t17 t27 ALE t38 CSx A23-A16 (A15-A8) BHE Address t6 t7 t54 t19 Read Cycle BUS t18 Address Data In t10 t8 t14 RD t44 t42 t12 t51 t52 t46 RdCSx t48 Write Cycle BUS t23 Address Data Out t56 t10 t8 WR, WRL, WRH t44 t42 t22 t12 t50 WrCSx t48 Figure 14-2 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group 48 1998-02 C164CI t5 t16 t25 ALE t38 t39 t40 CSx t17 A23-A16 (A15-A8) BHE t27 Address t6 t7 t54 t19 Read Cycle BUS t18 Address t9 Data In t11 RD t43 t15 t13 t45 RdCSx t51 t52 t47 t49 Write Cycle BUS t23 Address t9 Data Out t56 t11 t22 WR, WRL, WRH t43 t13 t45 t50 WrCSx t49 Figure 14-3 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group 49 1998-02 C164CI t5 t16 t25 t39 t40 t17 t27 ALE t38 CSx A23-A16 (A15-A8) BHE Address t6 t7 t54 t19 Read Cycle BUS t18 Address Data In t9 t11 RD t15 t13 t43 t45 RdCSx t51 t52 t47 t49 Write Cycle BUS t23 Address Data Out t56 t9 t11 WR, WRL, WRH t22 t13 t43 t45 t50 WrCSx t49 Figure 14-4 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group 50 1998-02 C164CI AC Characteristics CLKOUT VDD = 4.25 - 5.5 V; VSS = 0 V TA = -40 to +85 C for SAF-C164CI TA = -40 to +125 C for SAK-C164CI CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz min. max. min. max. Unit CC 50 50 2TCL 2TCL ns CLKOUT high time t29 t30 CC 19 - TCL - 6 - ns CLKOUT low time t31 CC 15 - TCL - 10 - ns CLKOUT rise time t32 CC - 4 - 4 ns CLKOUT fall time t33 CC - 4 - 4 ns CLKOUT rising edge to ALE falling edge t34 CC 0 + tA 10 + tA 0 + tA 10 + tA ns CLKOUT cycle time Semiconductor Group 51 1998-02 C164CI MUX/Tristate 3) Running cycle 1) t32 CLKOUT t33 t30 t29 t31 t34 ALE Command RD, WR 4) 2) Figure 15 CLKOUT Timing Notes 1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2) The leading edge of the respective command depends on RW-delay. 3) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles. 4) The next external bus cycle may start here. Semiconductor Group 52 1998-02 C164CI Package Outline 7max H 0.65 0.3 0.15 +0.08 -0.02 0.25 min 2 +0.1 -0.05 2.45 max Plastic Package, P-MQFP-80-1 (SMD) (Plastic Metric Quad Flat Package) 0.88 0.08 C 0.1 12.35 0.12 17.2 0.2 A-B D 80x 0.2 A-B D H 4x 14 1) M A-B D C 80x D B 14 1) 17.2 A 80 1 Index Marking 0.6x45 1) Does not include plastic or metal protrusions of 0.25 max per side Figure 16 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 53 Dimensions in mm 1998-02