TLC320AD77CDBG4 - Texas Instruments

TLC320AD77C

24ĆBit 96 kHz Stereo Audio Codec

1999 Mixed Signal Linear Products

Data Manual

Printed in U.S.A.

08/99 SLAS194

TLC320AD77C

24-Bit 96 kHz Stereo Audio Codec

Data Manual

SLAS194

August1999

Printed on Recycled Paper

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iii

Contents

Section Title Page

1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Functional Block Diagram 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Terminal Assignments 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Ordering Information 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Terminal Functions 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Functional Description 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 ADC Channel 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 DAC Channel 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Serial Interface 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Sampling Frequency 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Speed Mode Options 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Voltage Reference 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 ADC Analog Input 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 DAC Analog Output 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 Sigma-Delta ADC 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10 Decimation Filter 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11 Sigma-Delta DAC 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12 Interpolation Filter 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13 De-emphasis 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.14 Serial Interface Formats 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.14.1 MSB First Right/Left Justified Format 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.14.2 IIS-Compatible Serial Format 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.14.3 MSB Left Justified Serial Interface Format 2–4. . . . . . . . . . . . . . . . . . . . . . . . .

2.14.4 DSP Compatible Serial Interface Format 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15 Sampling Frequency Ranges 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16 Power Sequences 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.1 Initial Power Up 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.2 Power Down/Reset 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.3 Reinitialization Sequence 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.17 DAC De-Emphasis Filter 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.17.1 De-Emphasis Selection 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Specifications 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range 3–1. . . . .

3.2 Recommended Operating Conditions, TA = 25°C,

AVDD = DVDD = 3.3 V ± 10%, fs = 44.1 kHz 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Electrical Characteristics, TA = 25°C, AVDD = DVDD = 3.3 V ± 10%,

fs = 44.1 kHz 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.1 Static Digital Specifications, TA = 25°C,

AVDD = DVDD = 3.3 V ± 10% 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.2 ADC Digital Filter, TA = 25°C, AVDD = DVDD = 3.3 V ± 10%,

fs = 44.1 kHz 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.3 Analog-to-Digital Converter,

TA = 25°C, AVDD = DVDD = 3.3 V, fs = 44.1 kHz 3–2. . . . . . . . . . . . . . . . . . . .

3.3.4 DAC Interpolation Filter, TA = 25°C, AVDD = DVDD = 3.3 V + 10%,

fs = 44.1 kHz 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.5 Digital-to-Analog Converter, TA = 25°C, AVDD = 3.3 V, fs = 44.1 kHz,

Input = 1 Vrms Sine Wave at 1 kHz 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.6 Output Performance Data TA = 25°C, AVDD = DVDD = 3.3 V ± 10% 3–3. . . .

3.4 Serial Interface Switching Characteristics,

TA = 25°C, AVDD = DVDD = 3.3 V ± 10% 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 DSP Serial Interface Switching Characteristics,

TA = 25°C, AVDD = DVDD = 3.3 V ± 10% 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Parameter Measurement Information 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Application Information 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Single-Ended to Dif ferential External Analog

Front-End Circuit (fs = 44.1 kHz) 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 External Analog Back-End Circuit (fs = 44.1 kHz) 5–2. . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix A Mechanical Data A–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Illustrations

Figure Title Page

2–1 MSB First Right/Left Justified (for 16-, 20-, and 24-bits) 2–3. . . . . . . . . . . . . . . . . . . . . . . . .

2–2 IIS-Compatible Serial Format (for 16-, 20-, and 24-bits) 2–4. . . . . . . . . . . . . . . . . . . . . . . . .

2–3 MSB Left Justified Serial Interface Format (for 16-bits) 2–4. . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 DSP Compatible Serial Interface Format (for 16-bits) 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 De-Emphasis Characteristics 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 Master Clock Timing 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 Right/Left Justified, IIS, Left/Left Justified Serial Protocol Timing 4–1. . . . . . . . . . . . . . . . .

4–3 DSP Serial Port Timing 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 DAC Filter Overall Frequency Characteristics 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–5 DAC Digital Filter Passband Ripple Characteristics 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 ADC Digital Filter Characteristics 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–7 ADC Digital Filter Stopband Characteristics 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–8 ADC Digital Filter Passband Characteristics 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–9 ADC High Pass Filter Characteristics 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–1 Analog Front End (right channel) for 0.7 Vrms Input 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–2 Analog Back End (right channel) for 0.7 Vrms Output 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . .

5–3 Voltage Reference Connections 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

Table Title Page

2–1 Example Master Clock Frequency Rates 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–1

1 Introduction

The TLC320AD77C is a cost competitive stereo analog-to-digital (A/D) and digital-to-analog (D/A) 24-bit

delta-sigma converter for consumer applications which demand excellent audio performance. It has a wide

variety of serial input options including left justified, right justified, IIS, or DSP data formats for 16-, 20-, or

24-bit input/output data. It has an extremely wide range of sampling rates starting at 16 kHz and increasing

upwards to 96 kHz. Its internal bandgap design provides a very clean voltage reference. The TLC320AD77C

is primarily designed for mini-disks, audio/video receivers, musical instruments, and other end-equipments

requiring high-performance digital audio conversion.

1.1 Features

•24-Bit Delta Sigma Stereo ADC and DAC:

– 16-, 20-, or 24-Bit Input/Output Data

– Wide Range of Sampling Rates: 16 kHz to 96 kHz

– Master Clock: 256 fs or 384 fs

– 3.3-V Power Supply Operation

– Internal Bandgap Voltage Reference

– Economical 28-Pin DB (SSOP) Package

•Stereo ADC:

– Differential Input

– 128× Oversampling (in normal speed mode)

– High Performance: 100-dB Signal-to-Noise Ratio (SNR) (EIAJ), 100-dB Dynamic Range

– Digital High-Pass Filter

•Stereo DAC:

– Single-Ended Output

– 128× Oversampling (in normal speed mode)

– High Performance: 100-dB Signal-to-Noise Ratio (SNR) (EIAJ), 100-dB Dynamic Range

•Digital De-Emphasis:

– 32-kHz, 44.1-kHz, and 48-kHz Selection

•Special Features:

– High Jitter Tolerance

– Good Phase Characteristics

– Excellent Power Supply Rejection Ratio

1–2

1.2 Functional Block Diagram AVSS(REF)

ADC/DAC

Voltage Reference

VCOM VREFM VREFP VRFILT

ADC

Modulator

ADC

Decimation

Filter

ADC

HPF

Serial

Port

I/O

Interface

ADC

Modulator

ADC

Decimation

Filter

ADC

HPF

Analog

LPF

DAC

Interpolation

Filter

De-Emphasis

Digital

Modulator

Control

Analog

LPF

DAC

Interpolation

Filter

De-Emphasis

Digital

Modulator

Clock

Generator

DEM0

SDOUT

DEM1

SDIN

SCLK

LRCLK

MOD0

MOD1

MOD2

PDN_RSTB

SPDMODE

MCLK

AINRP

AINRM

AINLP

AINLM

AOUTR

AOUTL TEST

1–3

1.3 Terminal Assignments

AINLM

AINLP

VREFP

VREFM

VRFILT

AVSS(REF)

AVSS

MOD2

MOD1

MOD0

DVSS

SDIN

SDOUT

SCLK

AINRM

AINRP

AOUTR

VCOM

AOUTL

AVDD

TEST

SPDMODE

PDN_RSTB

DEM1

DEM0

DVDD

LRCLK

MCLK

DB PACKAGE

(TOP VIEW)

1.4 Ordering Information

PACKAGE

TASMALL OUTLINE

(DB)

0°C to 70°C TLC320AD77C

1–4

1.5 Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME NO.

I/O

DESCRIPTION

AINLM 1 I ADC analog differential negative input, left channel

AINLP 2 I ADC analog differential positive input, left channel

AINRM 28 IADC analog differential negative input, right channel

AINRP 27 IADC analog differential positive input, right channel

AOUTL 24 ODAC analog output, left channel

AOUTR 26 ODAC analog output, right channel

AVDD 23 Analog voltage supply

AVSS 7Analog voltage ground

AVSS(REF) 6 I Analog ground voltage reference

DEM0 18 IDe-emphasis selection

DEM1 19 IDe-emphasis selection

DVDD 17 Digital voltage supply

DVSS 11 Digital ground

LRCLK 16 ILeft/right clock

MCLK 15 IMaster clock

MOD0 10 ISerial interface selection

MOD1 9 I Serial interface selection

MOD2 8 I Serial interface selection

PDN_RSTB 20 IPower down/reset

SCLK 14 IShift or bit clock

SDIN 12 ISerial data DAC input

SDOUT 13 OSerial data ADC output

SPDMODE 21 ISampling frequency selection

TEST 22 Reserved, manufacturing test pin. Test should be connected to DVSS.

VCOM 25 O Common mode reference, provides a 1.5-V reference voltage (DAC only)

VREFM 4 O ADC/DAC negative reference voltage

VREFP 3 O ADC/DAC positive reference voltage

VRFILT 5 O Voltage reference low pass noise filter

2–1

2 Functional Description

2.1 ADC Channel

To produce excellent common-mode rejection of unwanted signals, the analog signal is processed

differentially until it is converted to digital data. A single-ended input signal must be converted into a

differential input and filtered with a single-pole antialiasing filter before entering the ADC input. (See

Section 2.7,

ADC Analog Input

). The ADC converts the signal into discrete output digital words in

2s-complement format, corresponding to the analog signal input. There is a high-pass filter to get rid of any

offset that the ADC modulator may have caused. These digital words, representing sampled values of the

analog input signal, are then clocked out the serial port, SDOUT, according to one of the eight allowable

serial port protocols.

2.2 DAC Channel

SDIN receives a serial data word whose length is specified by one of the eight allowable serial port protocols,

selected by the serial mode pins. The serial port latches the data on an edge of SCLK. The data goes through

the sigma-delta DAC comprised of digital interpolation filters and a seventh order, 1-bit digital modulator.

This oversampled signal is then passed through a switched capacitor FIR filter and RC low-pass filter which

smoothes the output waveform, and performs the differential to single-ended conversion. The DAC outputs

a stereo single-ended, inverted signal. This signal should be passed through an inverting,

pseudo-differential, external low-pass filter , where the VCOM reference is subtracted out. (See Section 2.8,

DAC Analog Output

2.3 Serial Interface

The digital serial interface consists of a serial port, shift clock (SCLK), left/right frame synchronization clock

(LRCLK), ADC-channel data output (SDOUT), and DAC-channel data input (SDIN). One of 8 different serial

port modes may be selected including IIS, right/left justified, left/left justified, and a DSP mode for word

lengths ranging from 16 to 24 bits. See Section 2.14,

Serial Interface Formats

for a description of serial

interface formats.

2.4 Sampling Frequency

The sampling or conversion frequency is designated by the MCLK rate by the following equation.

fs = MCLK frequency/ (256 or 384).

See Section 2.14,

Serial Interface Formats

for more information on the option of selecting an MCLK rate

of 256 fs or 384 fs.

2.5 Speed Mode Options

In normal-speed mode (SPDMOD = 0), sampling frequencies ranging from 16 kHz up to 48 kHz should be

used to achieve optimum performance.

In high-speed mode (SPDMOD = 1) the sampling frequencies are greater than 48 kHz and up to 96 kHz.

2.6 Voltage Reference

In order to achieve excellent noise rejection, a pseudo-differential reference is used with external capacitors

connected to a differential low-pass filter. The application schematic shows the necessary capacitors

needed to complete the filters found on the device. See Section 5,

Application Information

for the application

schematic for the voltage reference.

2–2

2.7 ADC Analog Input

The ADC accepts a differential input with a maximum value that does not exceed approximately 4 Vpp. See

Section 5.1,

Single-Ended to Differential External Analog Front-End Circuit

for a description of the

recommended external analog front end.

2.8 DAC Analog Output

The DAC outputs a single-ended signal with a max value of 0.7 Vrms. See Section 5.2,

External Analog

Back-End Circuit

for a description of the recommended back-end circuit.

2.9 Sigma-Delta ADC

The sigma-delta ADC is a third order modulator with 128 times oversampling in normal speed operation.

The ADC provides high resolution and low noise performance using over-sampling techniques.

2.10 Decimation Filter

The decimation filter reduces the digital data rate to the sampling rate. This is accomplished by decimating

with a ratio of 1:128. The output of this filter is a 2s complement 16-, 20-, 24-bit word clocking at the sample

rate selected.

2.11 Sigma-Delta DAC

The sigma-delta DAC is a seventh order modulator with 128 times oversampling. The DAC provides

high-resolution, low noise, from a 1-bit converter using over-sampling techniques.

2.12 Interpolation Filter

The interpolation filter resamples the digital data at a rate 128 times the incoming sample rate. The

high-speed data output is then used in the sigma-delta DAC.

2.13 De-emphasis

De-emphasis is supported for three sampling rates: 32 kHz, 44.1 kHz, and 48 kHz and selected with the

DEM0 and DEM1 pins.

2.14 Serial Interface Formats

The TLC320AD77C operates only in slave mode. It requires externally supplied MCLK (master clock), and

LRCLK (left/right clock), and SCLK (shift clock) inputs. There are two options for selecting the clock rates.

If a 384 fs MCLK rate is selected, then a LRCLK frame of 48 SCLKs must be supplied. If a 256 fs MCLK is

selected, then a LRCLK of 64 SCLKs must be supplied.

•A detection circuit automatically senses at which rate the MCLK is operating.

•The MCLK and SCLK must be synchronous and their edges must be at least 3 ns apart.

•If the LRCLK phase changes more than 10 MCLKs then the device automatically resets.

The TLC320AD77C is compatible with eight different serial interfaces. A vailable interface options are IIS,

right justified, left justified, and DSP frame. The following table indicates how the eight options are selected

using the MOD0, MOD1, and MOD2 pins. All serial interface options at either 16-, 20-, or 24-bits can operate

with SCLK at 48*fs or 64*fs except for the 16-bit DSP mode which should use SCLK = 64 fs.

2–3

MODE MOD2 PIN MOD1 PIN MOD0 PIN SERIAL INTERFACE SDIN (DAC)/SDOUT (ADC)

0 0 0 0 16-bit, MSB first, right justified/left justified

1 0 0 1 20-bit, MSB first, right justified/left justified

2 0 1 0 24-bit, MSB first, right justified/left justified

3 0 1 1 16-bit IIS

4 1 0 0 20-bit IIS

5 1 0 1 24-bit IIS

6 1 1 0 16-bit MSB first, left justified/left justified

7 1 1 1 16-bit DSP frame (see Note 1)

NOTE 1: For the 16-bit DSP frame use SCLK = 64 fs.

2.14.1 MSB First Right/Left Justified Format

Left Channel Right Channel

MSBX LSB MSBX

LSB MSB LSB

SDOUT

SDIN

LRCLK = fs

SCLK

MSB

LSB

Figure 2–1. MSB First Right/Left Justified (for 16-, 20-, and 24-bits)

Note the following characteristics of this protocol.

•Left channel data is valid when LRCLK is high.

•The SDIN (recorded data) data is justified to the trailing edge of LRCLK

•The SDOUT MSB (playback data) is transmitted at the same time as the LRCLK edge, and

captured at the very next rising edge of SCLK.

•If LRCLK phase changes by more than 10 MCLKs, then the device is automatically reset.

2–4

2.14.2 IIS-Compatible Serial Format

MSBX

SDIN

SCLK

MSBX

LSB

MSBX

LSB

Left Channel Right Channel

SDOUT

LRCLK = fs

Figure 2–2. IIS-Compatible Serial Format (for 16-, 20-, and 24-bits)

Note the following characteristics of this protocol.

•Left channel data is valid when LRCLK is low.

•SDIN is sampled with the rising edge of SCLK.

•SDOUT is transmitted on the falling edge of SCLK.

•If LRCLK phase changes by more than 10 MCLKs, then the device is automatically reset.

2.14.3 MSB Left Justified Serial Interface Format

MSB

LSB

Left Channel Right Channel

SDIN

SCLK

SDOUT

LRCLK = fs

LSB

Figure 2–3. MSB Left Justified Serial Interface Format (for 16-bits)

Note the following characteristics of this protocol.

•Left channel data is valid when LRCLK is high.

•The SDIN data is justified to the leading edge of LRCLK.

•The MSBs are valid at the same time as the LRCLK edge for SDOUT, and captured at the very

next rising edge of SCLK for SDIN.

2–5

2.14.4 DSP Compatible Serial Interface Format

15 14 13 15 14 130 0

Left Channel

(MSB = 15) Right Channel

(MSB = 15)

SDIN

SCLK

SDOUT

LRCLK = fs

Figure 2–4. DSP Compatible Serial Interface Format (for 16-bits)

Note the following characteristics of this protocol.

•MCLK = 256 Fs only

•SCLK = 64 times the sampling frequency.

•Serial data is sampled with the falling edge of SCLK.

•Serial data is transmitted on the rising edge of SCLK.

2.15 Sampling Frequency Ranges

The TLC320AD77C supports two sampling frequency ranges.

•When in the normal option ranging from 16 kHz up to 48 kHz, SPDMOD = low is used.

•When in the fast option ranging from greater than 48 kHz up to 96 kHz, SPDMOD = high is used.

NOTE:

The high speed clocks should never be applied while SPDMOD is low in order to

avoid glitches in the DAC and ADC outputs.

Table 2–1. Example Master Clock Frequency Rates

SAMPLING RATE FREQUENCY MCLK FREQUENCY

SPDMODE

(kHz) 256 fs384 fs

SPDMODE

32 8.192 MHz 12.2880 MHz 0

44.1 11.2896 MHz 16.9340 MHz 0

48 12.2880 MHz 18.432 MHz 0

64 16.384 MHz 24.576 MHz 1

88.2 22.579 MHz 33.868 MHz 1

96 24.576 MHz 36.864 MHz 1

2.16 Power Sequences

2.16.1 Initial Power Up

For initial power up, the ADC and DAC outputs are valid after the 150 ms settling time required for the analog

stages. Holding the power down pin low while ramping up the power supplies is recommended to avoid

glitches in the DAC output.

2–6

2.16.2 Power Down/Reset

The TLC320AD77C is capable of entering a stand-by mode at reduced power when no activity is required.

To initiate the reset sequence, PDN_RSTB is held low for a minimum of 10 ns. As long as the pin is held

low, the device is in the power-down state.

In order for the dynamic logic to be properly powered down, the clocks should not be stopped before the

PDN_RSTB pin goes low. Otherwise, the device may drain additional supply current.

2.16.3 Reinitialization Sequence

When PDN_RSTB is returned to high, the device begins a reinitialization sequence after all clocks are

active. The output data becomes valid after a minimum of 128 LRCLK cycles after the pin is pulled high.

During the initialization sequence the outputs of the DAC and ADC are invalid.

Any change in the control lines (MOD0, MOD1, MOD2, DEM0, DEM1, SPDMOD, PDN_RST) or phase shift

in LRCLK triggers the reinitialization sequence.

In order for the dynamic logic to be properly powered down, the clocks should not be stopped before the

PDN_RSTB pin goes low. Otherwise, the device may drain additional supply current.

2.17 DAC De-Emphasis Filter

De-emphasis is only supported for three sampling rates (fs): 32 kHz, 44.1 kHz, and 48 kHz in normal speed

operation. The DEM0 and DEM1 pins select the filter coefficients and enable or disable the filter . Figure 2–5

illustrates the de-emphasis filtering characteristics.

–10

3.18

(50 µs) 10.6

(15 µs)

f – Frequency – kHz

Response – dB

De-emphasis

Figure 2–5. De-Emphasis Characteristics

2.17.1 De-Emphasis Selection

De-emphasis control is achieved using the DEM1 and DEM0 pins. The pin control is defined in the following

table.

DEM 1 DEM 0 DE-EMPHASIS

0 0 32 kHz

0 1 44.1 kHz

1 0 48 kHz

1 1 Off

3–1

3 Specifications

3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range

(Unless Otherwise Noted)†

Analog supply voltage range, AVDD –0.3 V to 4.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital supply voltage range, DVDD –0.3 V to 4.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range –0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range –0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These

are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated

under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for

extended periods may af fect device reliability.

3.2 Recommended Operating Conditions, TA = 25°C,

AVDD = DVDD = 3.3 V ± 10%, fs = 44.1 kHz

MIN NOM MAX UNIT

Analog supply voltage, AVDD (see Note 1) 3 3.3 3.6 V

Digital supply voltage, DVDD (see Note 1) 3 3.3 3.6 V

Operating free-air temperature range, TA0 70 °C

NOTE 1: Voltages at analog inputs and outputs and A VDD are with respect to ground.

3.3 Electrical Characteristics, TA = 25°C, AVDD = DVDD = 3.3 V ± 10%,

fs = 44.1 kHz

PARAMETER MIN TYP MAX UNIT

Analog supply current Operating 30 mA

Power down (see Note 2) 150 µA

Digital supply current Operating 20 mA

Power down (see Note 2) 1µA

Power dissipation Operating 160 mW

Power down 360 µW

NOTE 2: If clocks are turned off.

3.3.1 Static Digital Specifications, TA = 25°C, AVDD = DVDD = 3.3 V ± 10%

PARAMETER MIN MAX UNIT

VIH High-level input voltage 2 3.6 V

VIL Low-level input voltage –0.3 0.8 V

VOH High-level output voltage (IO = –1 mA) 2.4 V

VOL Low-level output voltage (IO = 4 mA) 0.4 V

Ilkg Input leakage current –10 10 µA

CLLoad capacitance, SDOUT 50 pF

3–2

3.3.2 ADC Digital Filter, TA = 25°C, AVDD = DVDD = 3.3 V ± 10%, fs = 44.1 kHz

(see Notes 3 and 4)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ADC Decimation Filter (LPF)

Pass band 20 kHz

Pass band ripple ±0.01 dB

Stop band 24.1 kHz

Stop band attenuation 80 dB

Group delay 720 µs

ADC High-Pass Filter (HPF)

Pass band (–3 dB) 0.87 Hz

Deviation from linear phase 20 Hz to 20 kHz 1.23 degree

NOTES: 3. All the terms characterized by frequency, scale with the chosen sampling frequency , fs.

4. See Figure 4–6 through Figure 4–9 for performance curves on the ADC digital filter.

3.3.3 Analog-to-Digital Converter, TA = 25°C, AVDD = DVDD = 3.3 V, fs = 44.1 kHz

(see Note 3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SNR Signal-to-noise ratio (EIAJ) A-weighted 100 dB

Dynamic range A-weighted, –60 dB, 1 kHz 100 dB

Signal-to-noise + distortion ratio 20 Hz to 20 kHz 86 dB

Power supply rejection ratio 1 kHz, See Note 5 50 dB

Idle channel tone rejection 120 dB

Intermodulation distortion –80 dB

ADC crosstalk 100 dB

Overall ADC frequency response 20 Hz to 20 kHz –0.1 0.1 dB

Gain error 5%

Gain matching ±0.02 dB

Full-scale differential input voltage 3.6 Vpp

CMRR Common mode rejection ratio 100 dB

NOTES: 3. All the terms characterized by frequency, scale with the chosen sampling frequency, fs.

5. Measured with a 50 mV peak sine wave.

3.3.4 DAC Interpolation Filter, TA = 25°C, AVDD = DVDD = 3.3 V + 10%, fs = 44.1 kHz

(see Notes 3 and 6)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Pass band 0 20 kHz

Pass band ripple ±0.005 dB

Stop band 24.1 kHz

Stop band attenuation 28.8 kHz to 3 MHz 75 dB

Group delay 700 µs

NOTES: 3. All the terms characterized by frequency, scale with the chosen sampling frequency, fs.

6. See Figure 4–4 and Figure 4–5 for performance curves of the DAC digital filter.

3–3

3.3.5 Digital-to-Analog Converter, TA = 25°C, AVDD = 3.3 V, fs = 44.1 kHz,

Input = 1 Vrms Sine Wave at 1 kHz (see Note 3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SNR Signal-to-noise ratio (EIAJ) A-weighted 100 dB

Dynamic range A-weighted, –60 dB,

f = 1 kHz 100 dB

Signal-to-noise + distortion ratio 0 dB, 1 kHz 80 dB

Power supply rejection ratio 1 kHz 50 dB

Idle tone rejection 120 dB

Intermodulation distortion –75 dB

Frequency response –0.5 0.5 dB

Deviation from linear phase ±1.4 degree

DAC crosstalk 100 dB

Full-scale single-ended output voltage AVDD = 3.3 V 1.75 VPP

NOTE 3: All the terms characterized by frequency, scale with the chosen sampling frequency, fs.

3.3.6 Output Performance Data, TA = 25°C, AVDD = DVDD = 3.3 V ± 10%

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output Driver Loading

RLOutput load resistance, (see Note 7) 10 kΩ

CLOutput load capacitance 25 pF

RL(COM) Output load resistance, COM (see Note 8) 1 kΩ

CL(COM) Output load capacitance, COM

(see Note 8) 50 pF

RFILT internal resistance, RFILT

(see Note 9) 1 kΩ

NOTES: 7. The output load resistance is coupled through an ac coupled capacitor.

8. COM may vary during power down.

9. RFILT should never be used as a voltage reference.

3–4

3.4 Serial Interface Switching Characteristics, TA = 25°C,

AVDD = DVDD = 3.3 V ± 10%

PARAMETER MIN TYP MAX UNIT

f(SCLK) SCLK frequency 6.144 MHz

td(LRCLK) Delay time, LRCLK edge to SCLK rising 20 1/(128 ×fs) ns

td(SDOUT) Delay time, SDOUT valid from SCLK falling

(see Note 10) (1/(256×fs))+10 ns

tsu(SDIN) SDIN setup time before SCLK rising edge 20 ns

th(SDIN) SDIN hold time from SCLK rising edge 10 ns

f(LRCLK) LRCLK frequency 16 44.1 96 kHz

MCLK duty cycle 50%

SCLK duty cycle 50%

LRCLK duty cycle 50%

NOTE 10: Maximum of 50-pF external load on SDOUT

3.5 DSP Serial Interface Switching Characteristics, TA = 25°C,

AVDD = DVDD = 3.3 V ± 10% (see Note 11)

PARAMETER MIN TYP MAX UNIT

f(SCLK) SCLK frequency 6.144 MHz

td(FS) Delay time, SCLK rising to Fs 25 ns

tw(FSHIGH) Pulse duration, sync 1/(64×fs) ns

td(SDOUT) Delay time, SDOUT valid from SCLK rising

(see Note 12) (1/(256×fs))+10 ns

tsu(SDIN) SDIN and LRCLK setup time before SCLK falling

edge 20 ns

th(SDIN) SDIN and LRCLK hold time from SCLK falling edge 10 ns

SCLK duty cycle 50%

NOTES: 11. Burst mode is not supported.

12. T iming parameters for DSP format which samples on the falling edge

4–1

4 Parameter Measurement Information

twH(MCLK) twL(MCLK)

MCLK

Figure 4–1. Master Clock Timing

ÎÎÎÎÎÎÎ

td(SDOUT)

td(LRCLK)

tsu(SDIN) th(SDIN)

SCLK

LRCK

SDOUT

SDIN

Figure 4–2. Right/Left Justified, IIS, Left/Left Justified Serial Protocol Timing

SCLK

td(SDOUT)

th(SDIN)

ÎÎÎÎÎÎÎÎÎÎÎ

tsu(SDIN)

SDOUT

SDIN

LRCLK

td(FS)

tw(FSHIGH)

Figure 4–3. DSP Serial Port Timing

4–2

–60

–100

Amplitude – dB

–40

–20

f – Frequency – Hz

–80

s/2 1 fs2 fs3 fs4 fs5 fs

Figure 4–4. DAC Filter Overall Frequency Characteristics

–0.1

Amplitude – dB

0.05

0.1

–0.05

0f – Frequency – Hz

0.1 fs0.2 fs0.3 fs0.4 fs0.5 fs

Figure 4–5. DAC Digital Filter Passband Ripple Characteristics

–150

–200

Amplitude – dB

–50

–100

f – Frequency – Hz

02 f

s4 fs6 fs8 fs10 fs12 fs

Figure 4–6. ADC Digital Filter Characteristics

4–3

–60

–100

Amplitude – dB

–40

–20

–80

0f – Frequency – Hz

0.2 fs0.4 fs0.6 fs0.8 fs1 fs

Figure 4–7. ADC Digital Filter Stopband Characteristics

0.002

–0.002

Amplitude – dB

0.004

0.006

0.008

0f – Frequency – Hz

0.1 fs0.2 fs0.3 fs0.4 fs0.5 fs

Figure 4–8. ADC Digital Filter Passband Characteristics

–0.4

–1

Amplitude – dB

–0.2

0.2

–0.6

–0.8

0f – Frequency – Hz

1 fs2 fs3 fs4 fs

Figure 4–9. ADC High Pass Filter Characteristics

4–4

5–1

5 Application Information

5.1 Single-Ended to Differential External Analog Front-End Circuit

(fs = 44.1 kHz)

A single-ended to differential external analog front-end example circuit is shown in Figure 5–1. It biases the

input signal around A VDD/2 and applies the maximum input signal of 0.7 Vrms. The device sees a full-scale

differential input voltage of approximately 4 Vpp. For other maximum input signals, the ratio of R2/R1 can

be scaled accordingly to ensure a max ADC input of approximately 4 Vpp. As required by the ADC, R5, C4,

and R6 provide a single-pole low-pass antialiasing filter to attenuate unwanted frequencies. If the user

chooses to supply a single-ended input directly to the device (2 Vpp max), performance will be significantly

degraded.

10 kΩ

47 µF

AVDD/2

10 kΩ

10 pF

10 kΩ

10 pF

499 Ω

1000 pF

AINRM

AINRP

10 kΩ

5 V

GND

C1 8

U3:A

499 Ω

Antialiasing

Filter

Right Channel

Analog Input

0.7 Vrms 4 VPP

U3:B

211 2

Figure 5–1. Analog Front End (right channel) for 0.7 Vrms Input

5–2

5.2 External Analog Back-End Circuit (f s = 44.1 kHz)

For specified performance, the output should be taken between VCOM and AOUTR (or AOUTL). At pins

AOUTR and AOUTL the output is an inverted analog representation of the digital input signal. It is advisable

to add a low-pass filter to the output of the TLC320AD77C to eliminate high frequency noise >80 kHz. See

Figure 5–2 for the recommended analog back-end circuit. The output of this circuit provides the user with

a noninverted signal.

10 kΩ

AOUTR

VCOM

33 pF

R10

10 kΩ

5 V

GND

10 kΩ

33 pF

3.3 VA_Ground

(AD77 AVSS @ U2–7)

0.7 Vrms C20

47 µFR11

100 kΩ

3.3 VA_Ground

R12

221 Ω

Right Channel DAC

Output 0.7 Vrms

21 21 21

Figure 5–2. Analog Back End (right channel) for 0.7 Vrms Output

5–3

AVSS

AVDD

DVSS

DVDD

SCLK

MCLK

LRCLK

DEM0

DEM1

MOD2

MOD1

MOD0

SPDMODE

PDN_RSTB

TEST

AINRM

AINRP

AINLM

AINLP

SDIN

VREFM

VREFP

AVSS(REF)

VRFILT

SDOUT

AOUTR

VCOM

AOUTL

TLC320AD77

21 FB1 AVSS(REF)

VRFILT

2C10

15 µF

2C11

0.1 µF

2C9

0.1 µF

VREFP

2C8

0.1 µF

2C7

1 µF

VREFM

Vref Filter

Figure 5–3. Voltage Reference Connections

5–4

A–1

Appendix A

Mechanical Data

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

4040065 /C 10/95

28 PINS SHOWN

Gage Plane

8,20

7,40

0,15 NOM

0,63

1,03

0,25

12,90

12,30

10,50

8,50

Seating Plane

9,907,90

10,50

9,90

0,38

5,60

5,00

0,22

2016

6,50

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M

0,15

0°–8°

0,10

3,30

2,70

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

A–2

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

TLC320AD77CDB ACTIVE SSOP DB 28 50 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC320AD77CDBG4 ACTIVE SSOP DB 28 50 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC320AD77CDBR ACTIVE SSOP DB 28 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC320AD77CDBRG4 ACTIVE SSOP DB 28 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 11-Oct-2007

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm) W

(mm) Pin1

Quadrant

TLC320AD77CDBR SSOP DB 28 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Mar-2008

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLC320AD77CDBR SSOP DB 28 2000 346.0 346.0 33.0

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Mar-2008

Pack Materials-Page 2